优先排队电路的一点问题 希望大神来帮忙看下

module Priority(a,b,c,rst,clk,oa,ob,oc);
input a,b,c;
input rst,clk;
output oa,ob,oc;
reg oa,ob,oc;
always @(posedge clk or posedge rst) begin
if(rst)
begin
oa<=0;ob<=0;oc<=0;
end
if(a)
begin
oa<=1;ob<=0;oc<=0;
end
else if(!a&b)
begin ob<=1;oa<=0;oc<=0;
end
else if(!a&!b&c)
begin
oc<=1;oa<=0;ob<=0;
end
else
begin
oa<=0;ob<=0;oc<=0;
end end
endmodule
这段代码老是编译不过去 大神来帮忙看看把 刚学verilog没多久