2019991WARNING - CL318 :"E:\process\lattice\80_fxs_test1-1\RAM_DP.v":9:24:9:24|*Output Q has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
1166052WARNING - logical net 'cpu_fpga_bank/jdq_det/cnt_d_s_0_COUT0[4]' has no load.
61001101WARNING - Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
1166052WARNING - logical net 'cpu_fpga_bank/jdq_det/cnt_d_s_0_COUT0[4]' has no load.
61001101WARNING - Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
